October 15, 2014
The wonderful next big thing would be a flexible version of our television, laptop and cell phone. Thousands of Integrated Circuits (ICs) are hiding behind them as their core operators. However, nearly 95% of them are made on solid, rigid but brittle silicon and other inorganic semiconductor materials. They are extremely powerful as they provide unparalleled data processing speed (performance), energy efficiency (longer battery life time where applicable), multi-functionality (through ultra-large-scale-integration density) and low-cost (matured CMOS technology which relies on batch processing). But the challenge is they are not flexible so your television can be rolled back and carry in your suitcase or your laptop is not foldable to keep it in your pocket. Semiconductor industry has a process called back-grinding which can thin down any wafer from the back side but mechanical abrasive grinding. Although effective, the process is abrasive, damaging, wastes a whole wafer and often can produce a thinner version of the wafer which is not that thin (30 mm in reality is not that thin in flexible electronics world). Therefore, Electrical Engineering Program’s PhD Candidate Galo Torres Sevilla (born in Ecuador) has come up with a technique based on reactive ion etching to softly etch back the fully processed silicon wafer down to 10 mm. The ultra-thin silicon-on-insulator (SOI) wafer has nano-scale FinFETS (the most advanced transistor architecture commercialized by Intel Corporation). The achieved bending radius is 0.5 mm which is world record in context of bendability from pure mono-crystalline silicon (100) thin continuous film. The demonstrated technique is unique and pioneering to replace decade long exercised process technology like back grinding as it provides ultra-thin version of the substrate in a non-damaging and economical way. The device performance-energy efficiency-integration density are well preserved. It is to be noted that the Integrated Nanotechnology Lab has demonstrated world’s first fully flexible 3D non-planar FinFET CMOS early this year (published in highly respected Advanced Materials).
This seminal and pioneering work has been published in acclaimed peer reviewed journal ACS Nano which is an international forum for the communication of comprehensive articles on nanoscience and nanotechnology research at the interfaces of chemistry, biology, materials science, physics, and engineering. The impact factor of ACS Nano is 12.033 in 2013. The paper has already garnered global media attention: highlighted in nanotechweb as Technology Update: FinFETs go flexible, and highlighted in nanowerk as Spotlight: Flexible high-performance FinFETs with a bending radius of 0.5 mm.
The whole research work was carried out in KAUST (KAUST Advanced Nanofab – state of the art fabrication facility, Imaging and Characterization Lab and in the Integrated Nanotechnology Lab @ KAUST) by the KAUST graduate students only under the leadership of Associate Professor Muhammad Mustafa Hussain.