November 15, 2014
Conventional computing based on Von Neumann architecture has been shown to be approaching its limits in scalability and power consumption. If solved with contemporary machines, today’s applications in science and industry related to data analysis, pattern recognition and prediction would demand a huge computing power. In the era of ubiquitous sensing and data acquisition, a way to cheaply and power efficiently make sense of the collected ‘big data’ is of utmost importance. Here, human brain’s efficiency becomes the ultimate standard and inspiration for any future technology. Currently we need approximately 83,000 powerful processors to run for 40 minutes to simulate one second of brain activity with multiple orders of magnitude more power.
At the sensors lab
, students under the supervision of Prof. K.N. Salama are exploring new computing technologies miming the way our brains process and store data. In particular, the work of PhD student Mohammed Zidan
on memristors and Resistive memory arrays (ReRAM) is of great significance. ReRAM potentially address many of the challenges facing such a task. Using memristors to build neural networks reduces the required area significantly compared to classical circuits. ReRAM have also gained a lot of interest with the announcement of "The Machine"
, a server technology recently introduced by HP
fusing memory and storage through the use of resistive memories to form a one flat memory hierarchy. Resistive memory devices are very promising candidates replace the current storage technologies, due to their very high density, fast access time, and retainability. However, there are numerous challenges that need to be addressed before memristor devices genuinely replace the current technologies.
3D illustrations and equivalent circuits for (a,b) gateless
memristor memory cell and (c,d) gated memristor memory cell
In two recent papers at the prestigious IEEE Transaction on Nanotechnology (TNANO), we show how to solve some of the challenges facing such huge and flat memory array. We introduce for the first time, a closed-form solution for the memristor-based memory sneak paths without using any gating elements. The introduced technique fully eliminates the effect of sneak paths by reading the stored data using multiple access points and evaluating a simple addition/subtraction on the different readings. The new method requires fewer reading steps compared to previously reported techniques by HP, and has a very small impact on the memory density. We further extend the work to gated arrays that were thought to solve the sneak path problem. We show that leakage current ruins the memory readout process for high-density gated arrays, and analyze the trade-off between the array density and its power consumption. We propose a novel readout technique and its underlying circuitry, which is able to compensate for the transistor leakage current effect.
This work is described in detail in our recent two articles at IEEE TNANO that were highly praised by the reviewers:
1. M. Affan Zidan, H. Omran, A. Sultan, H. A. H. Fahmy, and K. N. Salama
Compensated Readout for High Density MOS-Gated MemristorCrossbar Array
IEEE Transaction on Nanotechnology (TNANO), vol. 14, no. 1, pp. 1-4, Jan 2015
2. M. A. Zidan, H. Fahmy, A. Eltawil, F. Kurdahi and K. N. Salama
Memristor Multi-Port Readout: A Closed-FormSolution for Sneak-Paths
IEEE Transactions on Nanotechnology (TNANO), vol.13, no.2, pp.274-282, March 2014
This work builds on our earlier widely cited Survey paper on Memristor Based Memory: The Sneak Paths Problem and Solutions that is recognized by ScienceDirect as one of the Top 25 hottest papers published in Microelectronics Journal in the period (January-March) and (April-June). The Top 25 provides lists of most read articles - counted by article downloads on ScienceDirect.
The IEEE Transactions on Nanotechnology (TNANO) publishes novel and important results in engineering at the nanoscale. It focuses on nanoscale devices, systems, materials and applications, and on their underlying science. It is an interdisciplinary journal that covers all areas of nanotechnology.
The Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems.
Mohammed Zidan is currently working toward the Ph.D. degree in the Electrical Engineering Program, King Abdullah University of Science and Technology (KAUST), Thuwal, Saudi Arabia. He received his MSc degree (ranked first) in electronics and communications engineering from Cairo University, Egypt, in 2010, and the B.Sc. degree (ranked first) in electronics and communications engineering from the Institute of Aviation Engineering and Technology (IAET), Egypt, in 2006. Before joining KAUST, he worked as a Teaching Assistant at the German University in Cairo, Egypt and the IAET. His research interests are memristor, memory, chaotic systems, and computer arithmetic. He is currently serving as a member of the working groups formulating the future IEEE Standards P1788 and P1680.4. Mohammed has 22 publications and 3 pending patents, which are cited more than 200 times. He received the IEEE Circuits and Systems (CAS) Society Pre-Doctoral Fellowship, which is offered annually to only two PhD students worldwide to recognize a young researcher.